Cadence INNOVUS System 15.20.000 | 2.7 Gb
Cadence Design Systems, Inc., the leader in global electronic design innovation, has presented 15.2 version of INNOVUS Implementation System, is optimized for industry-leading embedded processors, as well as for 16nm, 14nm, and 10nm processes, helping you get an earlier design start with a faster ramp-up.

With unique new capabilities in placement, optimization, routing, and clocking, the Innovus Implementation System features an architecture that accounts for upstream and downstream steps and effects in the design flow. This architecture minimizes design iterations and provides the runtime boost you'll need to get to market faster. Using the Innovus Implementation System, you'll be equipped to build integrated, differentiated systems with less risk.
The implementation system features a variety of key capabilities. Its massively parallel architecture can handle large designs and take advantage of multi-threading on multi-core workstations, as well as distributed processing over networks of computers.
Next-generation slack-driven routing with track-aware timing optimization addresses signal integrity early on and improves post-route correlation. The implementation system includes full-flow multi-objective technology, which makes concurrent electrical and physical optimization possible. It also shares a customizable flow via a common UI and user commands with synthesis and signoff tools. As a result, you can take advantage of robust reporting and visualization, improving your design efficiency and productivity.
Cadence's Tempus static timing analysis, Quantus parasitic extraction, and Voltus power integrity technologies are integrated with Innovus Implementation System. With this integration, you can accurately model the parasitics, timing, signal, and power integrity issues at the early stage of physical implementation and achieve faster convergence on these electrical metrics, resulting in faster design closure.
CCMPR01487809 NanoRoute results in SEGV when doing incremental postRoute optimization
CCMPR01487032 sroute crashes when custom shape is present in floorplan
CCMPR01486443 editMove crashes
CCMPR01484137 Bad partition pin placement
CCMPR01481008 Innovus crashes during ecoAddRepeater
CCMPR01480637 addStripe should jog around another power signal to connect to a ring
CCMPR01480389 Multi-cut ratio improvement
CCMPR01478975 EDI SEGV when using design browser to show schematic of unconnected net
CCMPR01477733 Hier ILM is not extracted in the lower-level block
CCMPR01477039 SEGV during optDesign -preCTS with old HECO flow
CCMPR01476521 SEGV during ecoRoute in 15.12 Innovus
CCMPR01476328 IMPESI-3201: Delay calculation fails before placement
CCMPR01475681 Wire data becomes dirty after TA-opt
CCMPR01475656 Pruning drops dominant scan view and ends with bad timing
CCMPR01475578 The editCopy command causes SEGV
CCMPR01474348 Power routing for 14 metal layers on a 7.3mm x 7.3mm design takes 8 hours using 8 CPUs
CCMPR01473 12 SEGV - Innovus 15.12 SEG faults while executing the deriveTimingBudget command
CCMPR01473686 Long runtime and large memory usage for the deriveTimingBudget command
CCMPR01473125 Feedthrough insertion creates LEC failure
CCMPR01472952 optDesign -postRoute hold fix fails to fix hold
CCMPR01472890 Crash with buffer size of select_obj
CCMPR01472733 Spare cells not spread in the module
CCMPR01470973 Suboptimal pin assignment
CCMPR01470610 optDesign -preCTS hangs
CCMPR01470492 Crash faced at globalDetailRoute with litho repair
CCMPR01469158 colorizeGeometry did not work and gave strange error
CCMPR01468938 SEGV occurs during NanoRoute due to assign description
CCMPR01468521 SDP placement violation -place_opt_design allows SDP groups to be placed outside the partition boundary
CCMPR01468305 User needs the ability to specify -vhdl -verilog and -system_verilog simultaneously
CCMPR01468302 update_name -restricted generates non-unique names
CCMPR01468002 EDI hangs when loading in OA library data
CCMPR01467352 M2 addstripe leaves gaps at standard cells
CCMPR01467242 optDesign -postRoute crashes on OA-based design
CCMPR01467185 Subsequent extractRC calls give different results (incremental triggered without changes)
CCMPR01465460 ERROR TA-1015 not understood
CCMPR01464755 RC correlation issue on clock nets
CCMPR01464571 SEGV at "routeDesign -trackOpt" with v15.12-e024_1
CCMPR01464152 Crash after placeBondPad
CCMPR01463059 SEGV routeDesign start of globalDetailRoute
CCMPR01462949 EDI14.2 crashed when saveDesign
CCMPR01462347 SEGV: routeDesign during diode insertion
CCMPR01462209 postCTS hold fix is degrading the setup time
CCMPR01461000 reportCongestion -trialRoute after place_opt_design with HUM crashes
CCMPR01459774 IO cannot be moved and flipped. Orientation is set.
CCMPR01459500 createPhysicalPin creates pin off Manufacturing Grid
CCMPR01458724 CCOpt SEGV during clock DRV phase.
CCMPR01458341 place_opt_design SEGV when using buffer, inverter MUSTJOIN output pin cells
CCMPR01457546 SEG fault in CCOpt during the parasitic update on BLACKADDER
CCMPR01455850 Innovus/EDI crashes during GDS stream out with text objects in design
CCMPR01455444 Innovus v15.11-s048_1 SEGV during BPA/globalDetailRoute
CCMPR01455363 Innovus graphic sluggish through EOD
CCMPR01454595 Crash during optDesign -postRoute during tQuantus extraction
CCMPR01453969 powerRouting is creating CutEolSpacing violations
CCMPR01453481 optDesign -preCTS crashes with 14.25
CCMPR01453426 SEGV during routeDesign
CCMPR01453072 NR crashes during globalroute extraction
CCMPR01452720 checkPlace shows violations when standard cells are placed abutting a macro
CCMPR01450994 Experiencing SEGV on the attachIOBuffer command
CCMPR01450923 Cut spacing within array getting changed with different stripe width
CCMPR01450550 Crash during optDesign -postRoute -hold
CCMPR01449876 write_ldb SEGV
CCMPR01447949 Crash during place_opt_design
CCMPR01446772 place_opt_design SEGV crash at AAE
CCMPR01446764 Tool crashes during initial detail routing
CCMPR01446038 IMPDB-2059: Typo in error message spelling ('becuase')
CCMPR01445802 SEGV during reset_ideal_network
CCMPR01444926 ecoDesign should preserve the ILM information when the new database is written back out
CCMPR01444345 The write_ldb command crashes.
CCMPR01444202 sroute does not connect follow pin over power domain
CCMPR01444186 saveDesign/write_sdc crash with Innovus
CCMPR01444156 Failed delay cal and ccopt crash
CCMPR01443214 addStripe does not use via as specified in the incremental VIARULE
CCMPR01443205 SEGV when reading OA technology library
CCMPR01443070 Crash when running routeDesign -trackOpt
CCMPR01442725 setAnalysisMode -aocv true causes ENCSYC-6122 warning
CCMPR01442311 Cannot delete power net with editDelete (strange verilog changes power net names)
CCMPR01441892 fcroute failed to route RDL with width 12
CCMPR01441747 NR crashes routing selected net
CCMPR01441571 CCOpt crashed during resize gate Resizing gates: ... 20% **DIAG
CCMPR01440610 Constraint tcl file causing crash when using init_design
CCMPR01439985 Incorrect supply being used on VDDO pins of iso-cells in Blackadder
CCMPR01439940 checkPlace should ignore cover cells no matter what the status is
CCMPR01439680 Enhance the htree placer to avoid placing the htree buffer under power grid in the same htree routing layers
CCMPR01438945 Negative Test: assembleDesign SEGVs when cloned instances specified multiple times with -blockData
CCMPR01438830 viaInitial claims cut does not fit in viaRule (ENCPP-547)
CCMPR01438829 INNOVUS: tQuantus SEGV during optDesign -postRoute
CCMPR01438459 CCOpt/CTS is not able to fix the slew violations
CCMPR01438266 'Assert' followed by SEGV whilst running optDesign -postRoute
CCMPR01438257 EDI: CCOpt clock debugger displays bug
CCMPR01437773 SEGV innovus 15.11-s045_1 in optDesign -preCTS running powerEffort ultraHigh
CCMPR01436833 Expose "edge" attribute for user-level db access
CCMPR01436802 Enhance global placement to handle edge constraints
CCMPR01436486 setDontUse -hinst should not need limited access keyword and be enabled only when actually used
CCMPR01436095 SEGV during optDesign -preCTS scan reordering
CCMPR01435968 Innovus partitioning creates non-compliant supply_set name
CCMPR01435113 OA saveDesign creates new ground signal
CCMPR01435082 Enhance dbViaCellRes to compute resistance of generated vias
CCMPR01433672 ERA - Innovus crashes when executing the read_power_rail_results command
CCMPR01433038 trialRoute -printSection does not print per layer information
CCMPR01432493 trimMetalFill creates rogue DRC-causing shapes that crashes verifyGeometry
CCMPR01432357 Q: How to get addStripe to trim fractional stripes at boundary
CCMPR01431102 Having problems with the EDI FlipChip router
CCMPR01429816 EDI crashed when create_spice_deck EDI14.23
CCMPR01429715 14.2 Nanoroute places via shorting to cell blockage covering pin, was ok in 14.1 and earlier
CCMPR01429628 SEGV during postroute optimization
CCMPR01429230 Encounter SEGV in refinePlace portion of placeDesign
CCMPR01429138 Expose via cell resistance for user-level db access
CCMPR01427971 Spare gate downsize issue
CCMPR01427706 Useless associate_supply_set and set_domain_supply_net commands
CCMPR01427149 SEGV faced at "routeDesign -trackOpt"
CCMPR01426994 addStripe creates the routing to the boundary when use "setAddStripeMode -trim_stripe core_boundary"
CCMPR01426942 Connecting the input output ports
CCMPR01426327 Partition UPF contains errors flagged by CLP
CCMPR01425786 addPowerSwitch creates overlap
CCMPR01425690 Crash during Postroute Optimization
CCMPR01425479 SEGV during place_opt_design using 14.24
CCMPR01425318 Issue with fcroute: not able to route PWR/GND nets
CCMPR01425276 CCOpt Introducing Assign Statements
CCMPR01424905 synthesize_ccopt_flexible_htrees results in error ENCCCOPT-1146
CCMPR01424801 INNOVUS v15.10-b054_1 - SEGV during saveDesign after place_opt_design
CCMPR01424781 SEGV during IQRC extraction in 14.23 version of EDI
CCMPR01424412 The suspend command is broken when -nowin is set
CCMPR01424333 do_extract_model is not generating correct power pins
CCMPR01423958 Command "deleteTieHiLo" takes around ~41 hrs
CCMPR01423674 EDI: ccopt_design -cts crashes with SEGV
CCMPR01422446 assembleDesign hangs
CCMPR01421863 ccopt_design -cts crashes
CCMPR01421547 14.23: routeDesign crashes without Stack Trace.
CCMPR01420772 lefOut should not include Via Metal fully covered by a Stripe
CCMPR01420345 verifyGeometry does not detect ENCLOSURE violations 615c
CCMPR01420256 SNet gets split during partitioning
CCMPR01419869 Encounter crashes
CCMPR01419160 deriveTimingBudget merge clone creates incorrect set_case_analysis
CCMPR01418468 OA-based design, verifyGeometry crashes when using EDI14.2 version
CCMPR01417761 ViaGen should pass via name prefix explicitly to DB with new API for via cell creation
CCMPR01417531 V12 layer confuses Replace Via in Encounter
CCMPR01417400 sroute -connect padPin does not work with metalfill routeblk
CCMPR01416545 createTQuantusModelFile got syntax error
CCMPR01415695 colorizeGeometry colors via differently from the stripe it connects to
CCMPR01415309 EDI verify_drc reports false V0 to V1 center to center cutSpacing violations
CCMPR01414150 addFiller should allow even VT distribution
CCMPR01413959 loadLefFile is not loading pin shapes
CCMPR01413305 verifyGeometry crashes when ENCLOSURE rules are repeated many times
CCMPR01412424 EDI14.23: ecoSwapSpareCell crashes when regular cell is swapped with Spare Physical Only cell.
CCMPR01412197 editSelectVia -floating_via -status SHIELD -net GNDD corrupts DB
CCMPR01411257 Encounter terminates with stack trace in saveTimingBudget
CCMPR01411197 checkFPlan erroneously flags FinFet grid violations in 65nm non-FinFet design
CCMPR01410589 timeDesign run time has grown 3X in EDI 14.24-e012 and later
CCMPR01410397 verify_drc unable to catch negative PRL violation reported by VG and signoff tool
CCMPR01410329 RC14.2(syntech) parser skips liberty attributes silently when these attributes are in bottom of .lib
CCMPR01409881 checkSdcCCD is missing an option to specify VDS_TIMING license
CCMPR01409790 useQrcOAInterface true not working when starting from verilog in reference of OA libraries
CCMPR01409520 CCOpt segmentation fault
CCMPR01407964 optDesign issues ENCOPT-3663 when leakage/dynamic power views specified
CCMPR01407886 verify_drc not catching errors caught by the PV tool
CCMPR01407033 Feedthrough insertion in non-unique design
CCMPR01406494 Long runtime for route step without timing optimization
CCMPR01406081 ccopt-cts SEGV with ILM (due to ILM HInst is not dont_touch)
CCMPR01405534 Time Budgeting creates false_paths on feedthrough ports
CCMPR01404840 EDI does not report on a missing timing library
CCMPR01404437 Assign statements remain in optDesign -postRoute -setup -hold DB from Innovus 'default' 15.10-b006_1 flow
CCMPR01403845 Run crashes during ccopt_design when ILM is used
CCMPR01403253 EDI (OA flow) exports Custom VIA in DEF with polygon with 4 coordinates
CCMPR01402852 optDesign with dynamic power opt writes temporary files to working directory and does not clean them up
CCMPR01402787 Post conditioning skew fixing leaves opens on the clock network leading to timing inaccuracies and poor slack
CCMPR01402443 globalNetConnect does not work when using the powerDomain option
CCMPR01402168 saveTestcase does not change some path variable in the SDC file
CCMPR01402005 addEndCap is not placing innercap triple height cells properly
CCMPR01401056 High runtime for writing DEF during RC extraction
CCMPR01400948 Request to speed up loading designs with CPF
CCMPR01400154 minProtrusionSpacing (JOGTOJOGSPACING) not detected depending on order definition
CCMPR01398850 EDI 14.20: checkPlace flags false Placement Blockage Violation.
CCMPR01397580 NR can choose optimal diode cell and dummy gate cell
CCMPR01395977 Filler cell insertion order not preserved
CCMPR01393964 Getting shrink factor value
CCMPR01393701 addIoRowFiller places filler cells in the core area and not in the IO rows.
CCMPR01388072 Poor handling of hierarchical gating in ccopt_design -cts
CCMPR01379408 checkPlace should not check cover cells
CCMPR01378260 Increase effectiveness of high strength soft guide for placing 2+ instances nearby
CCMPR01375391 Metal short issue in fillNotch, colorizeGeometry, verify_drc
CCMPR01375359 write_power_intent -1801: Bad UPF syntax
CCMPR01373745 addStripe to support LEF MACRO OBS DESIGNRULEWIDTH and SPACING rule
CCMPR01371142 ecoPlace does not find closest GA filler cell to replace
CCMPR01370424 Selecting all cells connected to a selected net
CCMPR01370416 Selecting all pins of a module
CCMPR01370129 Generated clock duty cycle definition is different for even divide_by factors not a power of 2
CCMPR01368215 Document "setSrouteMode connectBrokenCorePin 2" in the reference guide
CCMPR01366364 High-fanout net not being buffered by optDesign
CCMPR01365375 verify_drc is not reporting spacing violations
CCMPR01364397 Move the eco cell to an optimum location rather than the left edge of the filler cell
CCMPR01362861 PinAccess needs to consider the NDR of the net connecting to the pin
CCMPR01360756 Improve MAN page for update_constraint_mode -ilm_sdc_files
CCMPR01360755 Add the -reset option to setViaEdit command
CCMPR01359733 Spare gates are not placed randomly when using setPlaceMode -ignoreSpare true
CCMPR01359719 Floating PG Vias
CCMPR01358264 addTieHiLo crashes when run prior to routing
CCMPR01354950 reportPinDensityMap and queryPinDensity mistakes to calculate with rectilinear block
CCMPR01354883 ecoOaDesign ignores the setGenerateViaMode setting
CCMPR01353232 createPlaceBlockage -polygon -snaptosite does not create correct shapes
CCMPR01351645 Why placeDesign does not honor the fixed status of spare cells
CCMPR01351595 placeInstance does not place instance at the correct location
CCMPR01351068 Enhancement for addFiller to ignore cell padding
CCMPR01350674 LEC non-equivalent netlist after optDesign -preCTS
CCMPR01349556 ENCSYC-2100: ecoPlace -useSpare deletes logic during postMask ECO
CCMPR01346226 SEGV and tera-byte memory request placeSpareModule -moduleName SPARE_PACK_lac_top -util 0.5 -stepx 350 -stepy 350
CCMPR01344936 ecoPlace -useSpareCells should report instances used
CCMPR01342531 optdesign is not using AOB for feedthrough
CCMPR01341954 editPowerVia creates DRC with regular signals
CCMPR01336391 createRouteBlk -spacing not being honored for Special Routes
CCMPR01335664 Need single switch in EDI to ensure assign statement-free output
CCMPR01335479 clockDesign is not building clock tree
CCMPR01328384 optDesign crash - in verifyGeom code
CCMPR01325540 metal fill off manufacturing grid in EDI 14.12->14.14, on grid in 14.11 - 28nm
CCMPR01299709 Enhance dbGet to report VIARULE
CCMPR01242440 Incremental TQRC inaccurate on shielded net
CCMPR01242234 deleteFiller -keepFixed is giving false warning
CCMPR01208523 deleteSelectedFromFPlan calls deletePowerDomain with obsolete arguments
CCMPR01176933 savePartition -scanDef not saving PARTITION keyword in scan DEF file
CCMPR01095838 Improve "floorplan" command's Adjusting Core to Bottom messaging
CCMPR01087665 addFiller is not adding fillers in one power domain
CCMPR01073895 The ecoChangeCell command is taking too long
CCMPR01036634 Enhance specifyCellPad to add cell padding in all four diretions
CCMPR00894425 viaGen not honoring min spacing for large vias dropped on to thin macro power pins
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software and hardware, methodologies, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. Cadence reported 2007 revenues of approximately $1.6 billion, and has approximately 5,100 employees. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.

Name: Cadence INNOVUS System
Version: 15.20.000 Base Release
Supported Architectures: x86
Interface: english
System Requirements: Linux
Supported Operating Systems: RHEL 5, RHEL 6, SLES 11.0
Size: 2.7 Gb

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